Standard cells are designed based on power, area and performance. First step is cell architecture. Cell architecture is all about deciding cell height based on pitch & library requirements. We have to first decide the track, pitch, β ratio, possible PMOS width and NMOS width.

Clock Tree Synthesis (CTS) is one of the most important stages in PnR. CTS QoR decides timing convergence & power. In most of the ICs clock consumes 30-40 % of total power. So efficient clock architecture, clock gating & clock tree implementation helps to reduce power.

Routing is the stage after Clock Tree Synthesis and optimization where- Exact paths for the interconnection of standard cells and macros and I/O pins are determined. Electrical connections using metals and vias are created in the layout, defined by the logical connections present in the netlist.

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Physical design is process of transforming netlist into layout which is manufacture-able [GDS]. Physical design process is often referred as PnR (Place and Route) / APR (Automatic Place & Route). Main steps in physical design are placement of all logical cells, clock tree synthesis & routing.

Why CMOS? Output of all CMOS cells will be very close to rail-rail (may not be in case of Pass Transistor) With constant input to any cell, power dissipation is only due to leakage currents. Power dissipation increase if activity factor is more (Short circuit current + charging & discharging of load)

A System on Chip (SoC) is an integrated circuit that integrates all components of an electronic systems. It may contain digital, analog, mixed-signal, and radio-frequency modules—all on a single substrate. SoCs are very common in the mobile computing market because of their low power-consumption