Before starting the discussion on what is ASIC and what is FPGA, we will first learn about the basics that a VLSI enthusiast should know. Moore’s Law: Moore’s law is the observation that the number of transistors in a dense integrated circuit doubles about every two years.

Before starting the discussion on what is ASIC and what is FPGA, we will first learn about the basics that a VLSI enthusiast should know. Moore’s Law: Moore’s law is the observation that the number of transistors in a dense integrated circuit doubles about every two years.

GAA is somehow similar to FinFETs except the conducting channel is surrounded by gate all around. Thus we get better gate controllability over the channel. The channel shape can be square or any other polygon shape.

UART stands for Universal Asynchronous Receiver-Transmitter. It is commonly used in the microcontroller to communicate with the peripheral. An 8-bit serial data coming from the peripheral device is converted into the parallel form using serial to parallel conversion and parallel data coming from the CPU is converted using parallel to serial conversion.

CMOS technology uses both NMOS and PMOS transistors, The transistors are arranged in a structure formed by two complementary networks. Bulk CMOS is a chip built on a standard silicon wafer.

In 1965, Gorden Moore in his paper predicted that how number of transistors in integrated circuit get double in every 18 month. Even though in 1990, a new type of substrate named SOI (Silicon-on-insulator) was introduced which improved the speed and power consumption, the first integrated circuit transistor was fabricated on “Bulk” silicon wafers.

Silicon on insulator (SOI) refers to the use of a three layered substrate in place of conventional bulk silicon substrates. A thin layer of silicon is placed on top of an insulator such as silicon dioxide (SiO2) also known as a buried oxide layer.

Power is one of the most concerned factor in the lower node technologies due to sophisticated operation of a system at higher frequencies, complex functionalities, wireless applications and portability. Power dissipation has become one of the critical issues as it results in heating up of the device which in-turn affects the operation of a chip.

During Clock tree synthesis, buffers or inverters are added in the clock nets to achieve minimum Insertion delay and Skew, while meeting the clock DRV’s. Various optimizations are performed during CTS such as CCDO (Concurrent Clock and Data Optimization) and CTO (Clock Tree Optimization) .

What is STA ? Static timing analysis is one of the techniques used to verify the timing of a digital design. STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pins of the design.