What is the need of balanced buffers in clock path (Pulse Width Violation) ? Balanced buffers are preferred for clock tree synthesis. If unbalanced buffers (unequal rise & fall time) are used in CTS, then pulse width reduces & minimum pulse width violation occurs.

What are FinFETs?FinFETs are non-planar transistors built on SOI or Bulk substrate. FinFET describes any fin-based, multi-gate transistor architecture, regardless of the number of gates. 

Wire appears as a simple line in schematic diagrams, connecting two components. But they are equally important as transistors because they affect speed, power dissipation and reliability of the circuit.

PVT is abbreviation for Process, Voltage and Temperature. In order to make our chip to work in all possible conditions, like it should work in Siachen Glacier at -40°C and also in Sahara Desert at 60°C, we simulate it at different corners of process, voltage and temperature which IC may face after fabrication.

“Lot of freeware VLSI CAD tools work well on Ubuntu. Learning Linux, shell commands/scripts, awk, grep, sed, perl & shell will be very easy on Ubuntu, these are basic things any VLSI engineer has to know & this knowledge makes him faster”

Double click on electric to open it. A window will be displayed which will have File, Edit, Cell, Export,View, Window, Tools and Help options on the tool bar. On the left hand side pane, you will find a window which has three options namely : Layers, Components and Explorer. You will learn more about these options as we go ahead with the design.

Design Rule Check (DRC) determines whether the layout of a chip satisfies a series of recommended parameters called design rules. Design rules are set of parameters provided by semiconductor manufacturers to the designers, in order to verify the correctness of a mask set.

Routing optimization is a step performed after detailed routing in the flow. Inaccurate modeling of the routing topology may cause timing, signal integrity and logical design constraint related violations. This may cause conditions wherein fixing a violation would create other violations and many such scenarios may cascade to make it very difficult for timing closure with no timing DRCs.

The LEF file is the abstract view of cells. It only gives the idea about PR boundary, pin position and metal layer information of a cell. To get the complete information about the cell, DEF (Design Exchange Format) file is required. In this 3 sections are defined, i.e. technology, site, macros. In the technology part layers, design rules, via definitions and metal capacitance are defined.

Synthesis is process of converting RTL (Synthesizable Verilog code) to technology specific gate level netlist (includes nets, sequential and combinational cells and their connectivity).