Ways to fix setup violations: Setup violation occurs because of high delay in the data path or due to negative skew. Below are the ways to fix setup violation: Gate sizing Buffering

We hope you had a good understanding of Boolean Expressions which is available @ Boolean Expressions. In this blog, we will discuss on the simplification of boolean functions.

We hope you had a good understanding of Number Systems which is available @ Number Systems. For building hardware, we need logic gates, combinational circuits and sequential circuits which takes input in the form of binary numbers. The main building blocks to design combinational and sequential circuits are logic gates which is explained below.

We hope you had a good understanding of Logic Gates which is available @ Logic Gates. To reduce the logical complexities of any Boolean expression, a set of theorems have been developed which is explained below.

To start with VLSI skill development, we need to enhance our frontend skills. check the ASIC flow at ASICvsFPGA, which describes the frontend and backend flow for the full chip development. Frontend starts with specification gathering and architecture designing from the specifications gathered.

Before starting the discussion on what is ASIC and what is FPGA, we will first learn about the basics that a VLSI enthusiast should know. Moore’s Law: Moore’s law is the observation that the number of transistors in a dense integrated circuit doubles about every two years.

GAA is somehow similar to FinFETs except the conducting channel is surrounded by gate all around. Thus we get better gate controllability over the channel. The channel shape can be square or any other polygon shape.

UART stands for Universal Asynchronous Receiver-Transmitter. It is commonly used in the microcontroller to communicate with the peripheral. An 8-bit serial data coming from the peripheral device is converted into the parallel form using serial to parallel conversion and parallel data coming from the CPU is converted using parallel to serial conversion.

CMOS technology uses both NMOS and PMOS transistors, The transistors are arranged in a structure formed by two complementary networks. Bulk CMOS is a chip built on a standard silicon wafer.

In 1965, Gorden Moore in his paper predicted that how number of transistors in integrated circuit get double in every 18 month. Even though in 1990, a new type of substrate named SOI (Silicon-on-insulator) was introduced which improved the speed and power consumption, the first integrated circuit transistor was fabricated on “Bulk” silicon wafers.

Silicon on insulator (SOI) refers to the use of a three layered substrate in place of conventional bulk silicon substrates. A thin layer of silicon is placed on top of an insulator such as silicon dioxide (SiO2) also known as a buried oxide layer.

Power is one of the most concerned factor in the lower node technologies due to sophisticated operation of a system at higher frequencies, complex functionalities, wireless applications and portability. Power dissipation has become one of the critical issues as it results in heating up of the device which in-turn affects the operation of a chip.

During Clock tree synthesis, buffers or inverters are added in the clock nets to achieve minimum Insertion delay and Skew, while meeting the clock DRV’s. Various optimizations are performed during CTS such as CCDO (Concurrent Clock and Data Optimization) and CTO (Clock Tree Optimization) .

What is STA ? Static timing analysis is one of the techniques used to verify the timing of a digital design. STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pins of the design.

What is the need of balanced buffers in clock path (Pulse Width Violation) ? Balanced buffers are preferred for clock tree synthesis. If unbalanced buffers (unequal rise & fall time) are used in CTS, then pulse width reduces & minimum pulse width violation occurs.

What are FinFETs?FinFETs are non-planar transistors built on SOI or Bulk substrate. FinFET describes any fin-based, multi-gate transistor architecture, regardless of the number of gates. 

Wire appears as a simple line in schematic diagrams, connecting two components. But they are equally important as transistors because they affect speed, power dissipation and reliability of the circuit.

PVT is abbreviation for Process, Voltage and Temperature. In order to make our chip to work in all possible conditions, like it should work in Siachen Glacier at -40°C and also in Sahara Desert at 60°C, we simulate it at different corners of process, voltage and temperature which IC may face after fabrication.

“Lot of freeware VLSI CAD tools work well on Ubuntu. Learning Linux, shell commands/scripts, awk, grep, sed, perl & shell will be very easy on Ubuntu, these are basic things any VLSI engineer has to know & this knowledge makes him faster”

Double click on electric to open it. A window will be displayed which will have File, Edit, Cell, Export,View, Window, Tools and Help options on the tool bar. On the left hand side pane, you will find a window which has three options namely : Layers, Components and Explorer. You will learn more about these options as we go ahead with the design.

Design Rule Check (DRC) determines whether the layout of a chip satisfies a series of recommended parameters called design rules. Design rules are set of parameters provided by semiconductor manufacturers to the designers, in order to verify the correctness of a mask set.

Routing optimization is a step performed after detailed routing in the flow. Inaccurate modeling of the routing topology may cause timing, signal integrity and logical design constraint related violations. This may cause conditions wherein fixing a violation would create other violations and many such scenarios may cascade to make it very difficult for timing closure with no timing DRCs.

The LEF file is the abstract view of cells. It only gives the idea about PR boundary, pin position and metal layer information of a cell. To get the complete information about the cell, DEF (Design Exchange Format) file is required. In this 3 sections are defined, i.e. technology, site, macros. In the technology part layers, design rules, via definitions and metal capacitance are defined.

Synthesis is process of converting RTL (Synthesizable Verilog code) to technology specific gate level netlist (includes nets, sequential and combinational cells and their connectivity).

Standard cells are designed based on power, area and performance. First step is cell architecture. Cell architecture is all about deciding cell height based on pitch & library requirements. We have to first decide the track, pitch, β ratio, possible PMOS width and NMOS width.

Clock Tree Synthesis (CTS) is one of the most important stages in PnR. CTS QoR decides timing convergence & power. In most of the ICs clock consumes 30-40 % of total power. So efficient clock architecture, clock gating & clock tree implementation helps to reduce power.

Routing is the stage after Clock Tree Synthesis and optimization where- Exact paths for the interconnection of standard cells and macros and I/O pins are determined. Electrical connections using metals and vias are created in the layout, defined by the logical connections present in the netlist.