What is the need of balanced buffers in clock path (Pulse Width Violation) ? Balanced buffers are preferred for clock tree synthesis. If unbalanced buffers (unequal rise & fall time) are used in CTS, then pulse width reduces & minimum pulse width violation occurs.

Wire appears as a simple line in schematic diagrams, connecting two components. But they are equally important as transistors because they affect speed, power dissipation and reliability of the circuit.

PVT is abbreviation for Process, Voltage and Temperature. In order to make our chip to work in all possible conditions, like it should work in Siachen Glacier at -40°C and also in Sahara Desert at 60°C, we simulate it at different corners of process, voltage and temperature which IC may face after fabrication.