Choosing a VLSI Design Partner

By – SignOff Semiconductors

When the Partner Doesn’t Fit: What Really Goes Wrong in VLSI Design Engagements

We are a VLSI design services company. We have sat in a lot of partner evaluation meetings, and we have worked inside a lot of engagements once the contract is signed.

One thing we have noticed: a wrong partner choice almost never looks wrong on day one. The kickoff is friendly, the first weeks go fine, and the problems arrive quietly, months later, usually disguised as a schedule slip.

And what goes wrong depends heavily on how you engaged the partner. Hiring extra engineers, setting up a dedicated centre, and handing over a whole chip each carry their own kind of risk. Here is what each one looks like on the ground, from our side of the table.

Resource augmentation: when the capacity you bought turns into a training load

RA looks like the lowest-risk model. You keep control; you are only adding hands. That is exactly why the risk is easy to miss.

It usually starts with a strong interview. Then the engineer who joins is not quite the one you met, or is good but has never used your flow. Your senior engineers start spending their afternoons explaining scripts and reviewing basic work. On paper, the team grew by four. In practice, your best people lost a third of their week.

The second wave arrives around month four or five. An engineer leaves, often for a better offer elsewhere, and takes everything they learned about your design with them, because none of it was written down. The replacement needs weeks before they are truly productive, right when the schedule can least afford it.

None of this shows up as a line item. It shows up as your own team’s time, and as a milestone that quietly moves to the right.

ODC: when the team never stops being new

An offshore development centre is meant to get better every year as the team learns your designs. With the wrong partner, the opposite happens.

Year one is usually fine. By year two, the people who were there at the start have begun to move on. New faces keep arriving, the team is always halfway through onboarding, and the deep design knowledge you were paying to build never quite accumulates. Without a strong local technical lead, the team waits for tickets instead of spotting problems, and your managers end up running it remotely across time zones.

Then there is security, which tends to stay invisible until it doesn’t. A “dedicated” setup that turns out to share a network, or loose controls on data leaving the environment, can surface in one customer audit. In automotive or defence supply chains, a single finding like that can pause the engagement, or put your own customer relationships at risk.

When a customer wants to pay for progress: milestones

Milestone-based terms are fair to both sides: the customer pays for delivered work, and we get paid as we deliver. But they only work if both sides mean the same thing by “delivered.”

Anyone in design services knows how milestone disputes begin. The partner says RTL is complete. The customer opens it and finds lint warnings, open CDC issues and 70% coverage. Both sides are right by their own definition, and the relationship takes a hit it didn’t need to.

So we have learned to have one slightly tedious conversation before any contract is signed: define every milestone by evidence, not by a word. Not “RTL complete” but “RTL frozen, lint and CDC clean, 95% functional coverage on the agreed plan.” Not “timing closed” but “zero violations across the agreed corners, reports attached.” If a partner doesn’t bring this up, bring it up yourself.

When a customer needs a chip, not a team: turnkey

This is where AI startups, system companies and OEMs often come to us. They have a product and a specification; they don’t have, or want, a 60-person chip team.

Turnkey is the deepest trust a customer can place in a services partner, because they are buying an outcome. That is why we think every partner should be completely open about who does what. Many vendors are strong in one stage and subcontract others. There is nothing wrong with that, as long as the customer knows. Ask any partner plainly: “Who does DFT? Signoff? Package? Test?”

Two more questions we would ask in your seat. First: “Do you already have PDK access for our foundry and node?” Without that NDA in place, nothing else matters. Second: “What happens if first silicon has a bug?” A partner who has been through bring-up will talk about spare cells, metal-only fixes and debug plans. That answer tells you more than any tapeout count.

When a customer wants their own centre eventually: BOT

In build-operate-transfer, we build and run a team that will one day belong to the customer. It is an unusual business for a services company: success means handing over what we built.

The advice we give every BOT customer is simple: agree the exit on day one. When can you transfer, at what price, and what moves across: people, leases, licences? Discussed early, it is a friendly planning conversation. Left until year three, it becomes a negotiation, and that is not good for anyone, least of all the engineers.

Three things we would check, if we were in your seat

“Contributed to” is not “owned.” Every services company, describes its track record in the best possible light. “We worked on a 5nm tapeout” can mean closing full-chip timing, or it can mean two engineers fixing DRCs for a month. Both are honest; they are not the same. Ask what the partner actually owned.

Give us a real problem. The most useful evaluation we have taken part in was not a presentation. It was a working session on one of the customer’s actual issues. A customer learns more about how a team thinks in two hours than in a month of proposals, and so do we, about whether we are the right fit.

The cheapest rate is rarely the cheapest chip. We are not saying this to defend our pricing. One extra iteration, one missed shuttle slot or one respin can wipe out years of rate-card savings. Compare what the work will cost if things go wrong, not just what it costs per hour.
Signoff Semiconductors blog image

The one-glance version

If you need…The modelWhat a good partner should tell you, unprompted
Extra hands for a crunchResource augmentationHow they backfill when an engineer leaves
A long-term dedicated teamODCTheir attrition numbers, and an invitation to walk the floor
To pay only for verified progressMilestone-basedEvidence-based exit criteria for every milestone
A chip, not a teamTurnkeyWho does each stage, and their plan if silicon has a bug
Your own centre, eventuallyBOTThe transfer terms, on day one

Many of the engagements we see mix models, and that is often the smartest setup: the customer keeps RTL in-house, adds our engineers for verification, and hands us the backend turnkey. All that matters is that everyone has written down who owns what.

Where we fit

At SignOff Semiconductors, we work in all of these models: turnkey, ODC, BOT and resource augmentation, often with milestone-based terms. Our teams bring the experience of more than 100 tapeouts between them, on processes from 180nm to TSMC 2nm. For turnkey programmes, we take a chip from architecture or RTL through GDSII and into silicon, working with the foundry, package house and OSAT along the way.

But honestly, the most useful thing we can offer at the start is the conversation in this article.

Tell us what you are building and what you want to own. We will tell you which model we think fits, even if that means a smaller engagement, or a different partner.

Let’s talk: sales@signoffsemi.com

FAQs

What should we consider when choosing a VLSI design partner?

Evaluate the partner’s technical expertise, relevant tapeout experience, engagement model, team stability, security practices, and clarity on ownership and responsibilities. Ask what work they have actually owned, rather than relying only on overall tapeout numbers.

Resource augmentation can create hidden costs through onboarding, training, reviews, and knowledge loss when engineers leave. Evaluate the partner’s skill-matching process, backfill arrangements, and approach to documenting design knowledge.

Look for a stable team, strong local technical leadership, proactive problem-solving, and robust security and data-handling practices. Reviewing attrition numbers and visiting the centre can help assess the engagement’s long-term suitability.

Define milestones using measurable evidence rather than broad terms such as “RTL complete” or “timing closed.” Agree on deliverables, verification criteria, coverage targets, timing requirements, and the reports needed to demonstrate completion.

Ask who handles each stage, including architecture, RTL, DFT, signoff, packaging, and testing. Confirm PDK access for the target foundry and node, and discuss the partner’s plan for silicon bring-up, debugging, and addressing first-silicon issues.

In a BOT engagement, the partner builds and operates a dedicated team that is eventually transferred to the customer. Transfer timing, pricing, people, leases, licences, and knowledge transfer should be agreed upon at the beginning.

Look beyond headline tapeout numbers. Ask what the partner actually owned, such as full-chip timing closure, physical design, verification, or a specific part of the design flow. A technical working session using a real engineering problem can provide additional insight.

Not necessarily. A lower hourly rate may lead to higher overall costs if schedule delays, additional iterations, missed shuttle opportunities, or a respin occur. Evaluate the potential cost of delivery risks alongside the quoted rates.

Disclaimer: The content shared on this blog is for informational purposes only and is based on publicly available sources and industry insights. While we strive for accuracy, Signoff Semiconductor makes no representations regarding completeness or reliability. This content should not be considered professional advice.

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