Job Code – RTL-009
Job Description
- RTL designer (using Verilog or SystemVerilog) and good exposure to front-end design tools and flows.
- Good Knowledge in design of state machines, Datapath’s, arbitration and clock domain crossing logic.
- Good experience in ARM technologies and Integration of various subsystem blocks.
- Good experience in Low Power Design (UPF) design methodologies.
- Good experience in Synthesis, Constraint Development, Linting, CDC LEC and STA.
- Experience in scripting like Shell, Perl, Python and PHP
- Knowledge of low-speed bus protocols (like SPI/QSPI, I2C, I2S & etc) and high-speed serial protocols (PCIe/USB/Ethernet) will be plus.
- Good communication skills to work in a cross functional international team across various domains.
Requirements
Job Responsibilities
- In this role, the RTL Designer will be responsible to write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goal
- You work closely with engineers across performance modeling, validation, and implementation to meet all functional requirements, performance, power and area goals
- Leading, supervising, coaching, and mentoring a small team of RTL & DV engineers
- Mentor less experienced design engineers in implementation tasks to ensure compliance to specification, quality standards, and milestones
- Perform RTL design and Verification of digital macros, working from an architectural description
QUALIFICATIONS: BE/B.Tech/ME/M.Tech
EXPERIENCE: 4-10 years
Benefits
SignOff as an Organization believes that all Signoffites should have a peaceful Professional Engagement and has the following benefits as below for the Role.
Half Yearly Performance Review and Annual Salary Hikes
Group Health Insurance (Self, Family, and Parents)
Group Personal Accident
Emergency Loan Facility
Salary Advance Facility
Rewards & Recognition
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