Job Code: DFT-006

Location: Bangalore

Job Description:

1. Strong knowledge of the Tessent Shell environment and Tessent tools, specific emphasis on the following tools
   • Test Kompress / FastScan ATPG
   • MBIST
   • Boundary Scan
2. Knowledge on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow
3. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process
4. Experience in helping to debug failing scan patterns on the ATE is highly desirable.
5. Must be able to simulate and debug MBIST testbenches.

Required Qualification:

1. Bachelor’s degree in Electronics & Communication/Electrical & Electronics. Master’s degree in VLSI is preferred.
2. Experience 5-8 years of relevant experience
3. Proven ability to identify, assess and solve problems
4. Analytical with good interpersonal skills
5. Good Communication
6. Excellent team player
7. High Integrity
8. Mentoring Team Members
9. Prior experience of leading a team of 2-4 Engineers.

Signoff Semiconductors is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.