Routing is the stage after Clock Tree Synthesis and optimization where-
- Exact paths for the interconnection of standard cells and macros and I/O pins are determined.
- Electrical connections using metals and vias are created in the layout, defined by the logical connections present in the netlist.
After CTS, we have information of all the placed cells, blockages, clock tree buffers/inverters and I/O pins. The tool relies on this information to electrically complete all connections defined in the netlist such that-
- There are minimal DRC violations while routing.
- The design is 100% routed with minimal LVS violations.
- There are minimal SI related violations.
- There must be no or minimal congestion hot spots.
- The Timing DRCs are met.
- The Timing QoR is good.
The different tasks that are performed in the routing stage are as follows-
- Global Routing (also performed during placement stage).
- Track assignment.
- Detailed Routing.
- Search and Repair.
Goals of Routing
- Minimize the total interconnect/wire length.
- Maximize the probability that the tool can complete routing.
- Minimize the critical path delay.
- Minimize the number of layer changes that the connections have to make (minimizing the number vias).
- Complete the connections without increasing the total area of the block.
- Meeting the Timing DRCs and obtaining a good Timing QoR.
- Minimizing the congestion hotspots.
- SI driven: reduction in cross-talk noise and delta delays.
Routing Prerequisites
- All the design rules required during the routing stage must be defined in the technology file.
- The design must be placed and optimised. CTS and optimization should be complete.
- The PG nets must be pre-routed and physically connected to all macros and standard cells.
- The timing DRC violations and the timing QoR, estimated after CTS must be acceptable.
- The measured congestion should be tolerable.
- There should not be any ideal nets.
- High fanout nets should not be greater than the specified limit.
- Check for any optimization that needs to be done to fix any errors.
- Checking routability.
- After the placement and clock tree synthesis stage we must check if the design is ready for routing. The checks performed are as follows-
- Check if the ports of the standard cells are blocked i.e. the physical pins are not accessible.
- Checks for overlapping cells in the design. Overlapping causes pins to short and cause metal DRC violations.
- Check for pins underneath PG routes (they may be inaccessible and cause violations on metals) .
- Check if the ports of the top-level or macro cell are blocked and physically inaccessible.
- Check for pins that are outside the design boundary (Out-of-Boundary pins).
- Check for blocked PG ports.
- Check if there are frozen nets blocking ports.
- Check for blocked unconnected pins.
- Check if all pins in the design are on the routing tracks.
Routing Constraints
- Setting routing constraints guides the tool during routing. The constraints to be set are as follows-Set constraints to number of layer to be used during routing.
- Setting the maximum length for the routing wires.
- Set stringent guidelines for minimum width and minimum spacing.
- Set preferred routing directions to specific metal layers during routing.
- Constraining off-grid routing.
- Blocking routing in specific regions.
- Setting limits on routing to specific regions.
- Setting precedence to routing regions.
- Constraining the routing density.
- Constraining the pin connections.
- Restricting the degree of rerouting.
Global Routing
Global routing is a coarse-grain assignment of routes, which first partitions the routing region into tiles/rectangles called global routing cells (gcells) and decides tile-to-tile paths for all nets while attempting to optimize some given objective function (e.g., total wire length and circuit timing), but doesn’t make actual connections or assign nets to specific paths within the routing regions. By default, the width of a gcells is same as the height of a standard cell and is aligned with the standard cell rows.
Blockages, pins, and routing tracks inside the cell, dictate the routing capacity for every gcell. Then all nets assigned to the gcell are noted and the demand for the wire tracks in each gcell are calculated and overflows are reported.
Global routing is done in two stages namely-
- The initial routing stage, wherein the unconnected nets are routed and overflow for each gcell is calculated.
- Rerouting stages, where the congestion around gcells with net overflows are reduced by ripping off and rerouting the net.
After the initial routing stage and each rerouting stage, design statistics and congestion data are reported. A summary of wire length and via count at the end of the Global routing stage.
There are three types of Global Routing namely-
- Time-Driven Global Routing- The net delays are calculated before global routing.
- Cross-Talk Driven Global Routing- Avoids the creation of long tile-to-tile paths that run parallel on adjacent tracks.
- Incremental Global Routing- Performed using existing global route information.
Track Assignment
Track assignment is a stage wherein the routing tracks are assigned for each global routes. The tasks that are performed during this stage are as follows-
- Assigning tracks in horizontal and vertical partitions.
- Rerouting all overlapped wires.
Track Assignment replaces all global routes with actual metal layers. Although all nets are routed(not very carefully), there will be many DRC, SI and timing related violations, especially in regions where the routing connects the pins. These violations are fixed in the succeeding stages.
Detail Routing
The detailed router uses the routing plan laid by the router during the Global Routing and Track Assignment and lays actually metal to logically connect pins with nets and other pins in the design. The violations that were created during the Track Assignment stage are fixed through multiple iterations in this stage.
The main goal of detailed routing is to complete all of the required interconnect without leaving shorts or spacing violations. The detailed routing starts with the router dividing the block into specific areas called switch boxes or Sbox, which are generally expressed in terms of gcells. These boxes align with the gcell boundary. For example, a 3×3 Sbox is a box which encompass 9 gcells.
Search And Repair
The search-and-repair stage is performed during detailed routing after the first iteration. In search-and-repair, shorts and spacing violations are located and rerouting of affected areas to fix all possible violation is executed.
……. to be continued.
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