Job Summary :

Looking for AMS Verification Engineers with 4-5 years exp. strong knowledge of mixed signal verification fundamentals Experience with behavioral modelling of analog blocks like switching converters and LDO’s using SV/Verilog/Verilog-AMS/Verilog Strong background in verification fundamentals, verification planning and environment development is must Experience with SV assertions development Should be process oriented and have passion for scripting and automation Should have good soft skills and experience of working collaboratively in cross-site environment

Job Description

• Good knowledge of Basic Analog/Digital concepts.
• Good knowledge of Verilog/SV concepts.
• Experience in using spice simulation and digital simulation tools like Virtuoso, primesim, Finseim, Hspice, Xcellium, Simvision, Waveview.
• Experience in understanding Spice simulation environment/Digital simulation environment, able to debug analog/digital design related issues.
• Work experience in co-sim simulation designs is a plus.
• Good scripting skills using perl, python is a plus.
• Must possess good communication skills and ability to work well in a team.

Requirements

• Bachelor’s with 5+ years of work experience or Post Graduate Degree in Electronics Engineering or related engineering field with 3+ years of working experience is required.

Benefits

• As per SignOff Policy