Job Description:

• Good understanding of basic VLSI concepts: CMOS, IC Fabrication, FINFET, RC Network etc.
• Expert in different Layout approaches associated with AMS/Digital/IO/Standard Cells/Memory Layout etc. starting from floor-plan to closure with knowledge of basic circuits, matching constraints, design-driven constraints expected.
• Hands on experience in AMS layout (For example: PLL, RX, TX, Data converters, Regulator etc.) and in Custom Standard cells and logic design cells’
• Experience in lower nodes including FINFET is preferred
• Familiar and hands on experience on reliability issues such as EM/IR, ESD, LUP etc.
• Good understanding of layout effects with related constraints in speed, parasitic, area, power and other second order effects.
• Strong debugging and problem-solving skills in resolving layout design challenges and physical verification issues.
• Self-motivated team player with good communication skills to adapt to dynamic environment are essential.
• Experience in scripting (tcl, PERL etc.) and automation is a plus.
• Independently work to determine methods and procedures on new technologies to mentor, co-ordinate activities of others as Team Lead. Good at documenting and presenting.
• Flexible to work in client location and ODC.

Requirements

Qualifications

• Education: BE/B.Tech/M.Sc. in ECE/EEE or M.Tech VLSI
• Experience: 8 to 12 years
• Skills: Technical problem solving, Communication Skills, Presentation Skill, Leading Team, Mentoring Junior Engineer

Benefits

• As per SignOff Policy