Job Code : FCT (STA) L 001

• Opportunity to work with talented and passionate STA engineers and create designs that push the envelope on performance, energy efficiency and scalability
• At Signoff, you will are offered a fun, creative and flexible work environment, with a shared vision to build products to change the world

• The candidate will be responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs.
• Full chip timing analysis from early investigation to final implementation and tape out.
• Propose or develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure.
• Work with architects and logic designers to generate block and full chip timing constraints.
• Analyse scenarios and margin strategies with Synthesis & Design team.
• Partner with physical design teams to close and sign off the designs through PnR and ECO cycles.

• Hands-on experience in ASIC timing constraints generation and timing closure.
• Expertise and advanced knowledge of industry standard timing EDA tools (Prime Time, StarRC etc.).
• Deep understanding and experience in timing closure of various functional and test modes
• Expertise in deep-sub micron processes (Crosstalk delay, noise glitch, POCV, IR-STA).
• Proficient in scripting (TCL, Perl, Python, csh/bash).
• Problem solver, Efficient written and verbal communication, Excellent organization skills and Mentorship quality.
• Self starter and highly motivated.
• Ability to work cross-functionally with various teams and be productive under aggressive schedules.

• PhD, Masters or Bachelors Degree in EE, EECS or CS.