Silicon on insulator (SOI) refers to the use of a three layered substrate in place of conventional bulk silicon substrates. A thin layer of silicon is placed on top of an insulator such as silicon dioxide (SiO2) also known as a buried oxide layer.
Power is one of the most concerned factor in the lower node technologies due to sophisticated operation of a system at higher frequencies, complex functionalities, wireless applications and portability. Power dissipation has become one of the critical issues as it results in heating up of the device which in-turn affects the operation of a chip.
During Clock tree synthesis, buffers or inverters are added in the clock nets to achieve minimum Insertion delay and Skew, while meeting the clock DRV’s. Various optimizations are performed during CTS such as CCDO (Concurrent Clock and Data Optimization) and CTO (Clock Tree Optimization) .
What is STA ? Static timing analysis is one of the techniques used to verify the timing of a digital design. STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pins of the design.
What is the need of balanced buffers in clock path (Pulse Width Violation) ? Balanced buffers are preferred for clock tree synthesis. If unbalanced buffers (unequal rise & fall time) are used in CTS, then pulse width reduces & minimum pulse width violation occurs.
What are FinFETs?FinFETs are non-planar transistors built on SOI or Bulk substrate. FinFET describes any fin-based, multi-gate transistor architecture, regardless of the number of gates.
Wire appears as a simple line in schematic diagrams, connecting two components. But they are equally important as transistors because they affect speed, power dissipation and reliability of the circuit.
PVT is abbreviation for Process, Voltage and Temperature. In order to make our chip to work in all possible conditions, like it should work in Siachen Glacier at -40°C and also in Sahara Desert at 60°C, we simulate it at different corners of process, voltage and temperature which IC may face after fabrication.
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Double click on electric to open it. A window will be displayed which will have File, Edit, Cell, Export,View, Window, Tools and Help options on the tool bar. On the left hand side pane, you will find a window which has three options namely : Layers, Components and Explorer. You will learn more about these options as we go ahead with the design.