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			<title>Chiplets Reshaping Semiconductor Design: Cost &amp; Performance</title>
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			<pubDate><![CDATA[Tue, 27 Jan 2026 20:28:48 +0000]]></pubDate>
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			<title>SignOff Semicondcutors at IESA Vision Summit 2026</title>
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			<pubDate><![CDATA[Wed, 04 Mar 2026 06:20:40 +0000]]></pubDate>
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			<pubDate><![CDATA[Tue, 27 Jan 2026 20:25:35 +0000]]></pubDate>
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			<title>Getting started with Ubi, std cell design &#038; layout #2</title>
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			<guid><![CDATA[https://signoffsemiconductors.com/pvt-rc-variation-ocv/]]></guid>
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			<title>SignOff at IESA Vision Summit 2026</title>
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			<pubDate><![CDATA[Mon, 16 Feb 2026 19:11:59 +0000]]></pubDate>
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			<title>UPF</title>
			<pubDate><![CDATA[Tue, 10 Feb 2026 16:53:22 +0000]]></pubDate>
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			<title>Post CTS Optimization</title>
			<pubDate><![CDATA[Tue, 10 Feb 2026 16:53:16 +0000]]></pubDate>
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			<title>Getting started with Ubi, std cell design &#038; layout #1</title>
			<pubDate><![CDATA[Tue, 10 Feb 2026 16:52:58 +0000]]></pubDate>
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					<item>
			<guid><![CDATA[https://signoffsemiconductors.com/manoj-subramanian/]]></guid>
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			<title>Manoj Subramanian</title>
			<pubDate><![CDATA[Sat, 07 Feb 2026 13:55:42 +0000]]></pubDate>
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					<item>
			<guid><![CDATA[https://signoffsemiconductors.com/asic-vs-fpga/]]></guid>
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			<title>ASIC vs FPGA</title>
			<pubDate><![CDATA[Tue, 27 Jan 2026 20:23:10 +0000]]></pubDate>
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			<title>FinFET-1</title>
			<pubDate><![CDATA[Tue, 10 Feb 2026 16:53:17 +0000]]></pubDate>
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			<guid><![CDATA[https://signoffsemiconductors.com/introduction-to-sdc/]]></guid>
			<link><![CDATA[https://signoffsemiconductors.com/introduction-to-sdc/]]></link>
			<title>Introduction to SDC</title>
			<pubDate><![CDATA[Tue, 27 Jan 2026 20:22:04 +0000]]></pubDate>
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			<title>Announcements / News Updates</title>
			<pubDate><![CDATA[Mon, 09 Mar 2026 06:13:11 +0000]]></pubDate>
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			<title>Leadership</title>
			<pubDate><![CDATA[Fri, 09 Jan 2026 10:08:43 +0000]]></pubDate>
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			<title>CMOS Basics &#038; Process Overview</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<title>IC Design &amp; Flow Overview</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<title>Floorplan</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<title>Routing</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<title>Placement &#038; Optimization</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<guid><![CDATA[https://signoffsemiconductors.com/clock-tree-synthesis-1/]]></guid>
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			<title>Clock Tree Synthesis</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<title>Routing optimization and Chip Finishing</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<title>LEF, DEF &#038; LIB</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<title>Standard Cell Library</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:13 +0000]]></pubDate>
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			<title>Number Systems</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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			<title>Boolean Expressions-1</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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			<guid><![CDATA[https://signoffsemiconductors.com/boolean-expressions-2/]]></guid>
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			<title>Boolean Expressions-2</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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			<title>Logic Gates</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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			<title>Gate All Around FET</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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			<title>Communication Protocols</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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			<title>FinFET-2 (Multi-Gate FinFET)</title>
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			<title>Bulk CMOS</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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			<title>Silicon On Insulator ( SOI )</title>
			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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			<pubDate><![CDATA[Fri, 02 Jan 2026 07:02:12 +0000]]></pubDate>
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